Due to advancing semiconductor processing technology, integrated circuits have greatly increased in functionality and complexity. For example, programmable devices such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs), can incorporate ever-increasing numbers of functional blocks and more flexible interconnect structures to provide greater functionality and flexibility.
FIG. 1 is a simplified schematic diagram of a conventional FPGA 110. FPGA 110 includes user logic circuits such as input/output blocks (IOBs) 160, configurable logic blocks (CLBs) 150, and programmable interconnect 130, which contains programmable switch matrices (PSMs). Each IOB includes a bonding pad (not shown) to connect the various user logic circuits to pins (not shown) of FPGA 110. Some FPGAs separate the bonding pad from the IOB and may include multiple IOBs for each bonding pad. Other FPGA arrangements are known to those of skill in the art.
Configuration port 120 is typically coupled to external pins of FPGA 110 through various bonding pads to provide an interface for external configuration devices to program the FPGA. Each CLB can be configured through configuration port 120 to perform a variety of functions. Programmable interconnect 130 can be configured to provide electrical connections among the various CLBs and IOBs by configuring the PSMs and other programmable interconnect points (PIPS, not shown) through configuration port 120. IOBs can be configured to drive output signals to the corresponding pin of the FPGA, to receive input signals from the corresponding pins of FPGA 110, or to be bi-directional.
FPGA 110 also includes dedicated internal logic. Dedicated internal logic performs specific functions and can only be minimally configured by a user. Configuration port 120 is one example of dedicated internal logic. Other examples may include dedicated clock nets (not shown), delay lock loops (DLL) 180, block RAM (not shown), power distribution grids (not shown), and boundary scan logic 170 (i.e., IEEE Boundary Scan Standard 1149.1, not shown).
FPGA 110 is illustrated with 16 CLBs, 16 IOBs, and 9 PSMs for clarity only. Actual FPGAs may, for example, contain thousands of CLBs, thousands of PSMs, hundreds of IOBs, and hundreds of pads. Furthermore, FPGA 110 is not drawn to scale. For example, a typical pad in an 10B may occupy more area than a CLB, or PSM. The ratio of the number of CLBs, IOBs, PSMs, and pads can also vary. Also, other FPGA architectures are known to those of skill in the art.
FPGA 110 also includes dedicated configuration logic circuits to program the user logic circuits. Specifically, each CLB, 10B, and PSM contains a configuration memory cells (not shown) that must be configured before each CLB, 10B, or PSM can perform a specified function. Typically, the configuration memory cells within an FPGA use static memory cells. The configuration memory cells of FPGA 110 are connected by a configuration structure (not shown) to configuration port 120 through a configuration access port (CAP) 125. A configuration port (a set of pins used during the configuration process) provides an interface for external configuration devices to program the FPGA. The configuration memories are typically arranged in rows and columns. The columns are loaded from a frame register which is in turn sequentially loaded from one or more sequential bitstreams. (The frame register is part of the configuration structure referenced above.) In FPGA 110, configuration access port 125 is essentially a bus access point that provides access from configuration port 120 to the configuration structure of FPGA 110.
FIG. 2 illustrates a conventional method used to configure FPGA 110. Specifically, FPGA 110 is coupled to a configuration device 230, such as a serial programmable read only memory (SPROM), an electrically programmable read only memory (EPROM), or a microprocessor. Configuration port 120 receives configuration data, usually in the form of a configuration bitstream, from configuration device 230. Typically, configuration port 120 contains a set of mode pins, a clock pin and a configuration data input pin. Configuration data from configuration device 230 is typically transferred serially to FPGA 110 through a configuration data input pin. In some embodiments of FPGA 110, configuration port 120 comprises a set of configuration data input pins to increase the data transfer rate between configuration device 230 and FPGA 110 by transferring data in parallel. Further, some FPGAs allow configuration through a boundary scan chain.
Many FPGA designs have become so sophisticated that they can be configured to include processing cores. For example, FIG. 3 illustrates a FPGA design using FPGA 110, where the configuration logic blocks in the top left corner have been configured into a processing core 310. As explained above, FPGA 110 is greatly simplified. Actual FPGAs may need hundreds of configuration logic blocks to implement a processing core. In some FPGAs a processing core is embedded directly on the FPGA without use of configurable logic. In general processing core 310 would be coupled to an external memory system. In many situations, access to on-chip memory may enhance the performance of processing core 310. While the configuration logic blocks of many FPGA can be configured to provide a limited amount of read/write memory, including a large number of dedicated on-chip memory cells on an FPGA may not be cost effective because many designs would not require the on-chip memories. Thus, there is a need for a circuit or a method to provide on-chip memory on an FPGA without increasing the cost of the FPGA.